This invention relates to a semiconductor integrated circuit device and a process for fabricating a semiconductor integrated circuit device and, more particularly, to a semiconductor integrated circuit device having a protection circuit implemented by a bipolar transistor and a process for fabricating it.
The integration density of a semiconductor integrated circuit device has been increased, and, accordingly, the circuit components have been miniaturized. Circuit components of an integrated circuit are usually isolated as shown in FIG. 1A. The standard isolation is achieved by an insulating layer 50 grown along a boundary area between n-type impurity regions formed in a p-type silicon substrate 52. However, the standard isolation can not sufficiently isolate the miniature circuit components, and a shallow trench isolation is used for the miniature circuit components. The shallow trench isolation is shown in FIG. 1B. The p-type silicon substrate 52 is partially removed so that a shallow trench 51 is formed in the boundary area between the n-type impurity regions. Though not shown in FIG. 1B, the shallow trench is filled with insulating material, and the insulating material isolates the n-type impurity regions from one another.
Static charge is liable to destroy the miniature circuit components, and a protection circuit is incorporated in the semiconductor integrated circuit device against the static charge. A lateral n-p-n type bipolar transistor is a circuit component of the protection circuit, and has an n-type emitter region and an n-type collector region laterally spaced from each other. The surface portion of the p-type silicon substrate serves as a p-type base region between the n-type emitter region and the n-type collector region. Thus, the lateral n-p-n type bipolar transistor has the structure similar to that shown in FIG. 1B. When the n-type emitter region is isolated from the n-type collector region by means of the shallow trench isolation, the insulating material in the shallow trench increases the effective base width, and the wide base width causes the clamp voltage to be high. As a result, when the static charge is applied, the lateral n-p-n type bipolar transistor does not promptly turn on, and the static charge tends to reach the circuit components of an integrated circuit to be protected by the protection circuit.
A solution is proposed in Proceedings of EOS/ESD Symposium, 1992, pages 277 to 288. FIG. 2 illustrates the prior art vertical diode disclosed in the Proceedings. Reference numeral 70 designates a p-type silicon substrate. Two n-type wells 71 and 72 are formed in the p-type silicon substrate 70, and are spaced from one another. Shallow trench isolations 73 are employed in the prior art vertical diode. A single n-type impurity region 74 and two n-type impurity regions 74 are formed in a surface portion of the n-type well 71 and a surface portion of the other n-type well 72, respectively, and a p-type impurity region 75 is formed in a surface portion of the n-type well 72 between the n-type impurity regions 74 in the n-type well 72. A p-type impurity region 75 is further formed in a surface portion of the p-type silicon substrate 70 between the n-type well 71 and the other n-type well 72. The shallow trench isolations 73 are provided between the p-type silicon substrate 70, the n-type impurity region 74, the p-type impurity region 75, the n-type impurity region 74, the p-type impurity region 75, the n-type impurity region 74 and the p-type silicon substrate 70.
A power supply line PW is connected to the n-type impurity regions 74 in the n-type well 72, and the power voltage is applied to the n-type well 72. A ground line GND is connected to the p-type impurity region 75 between the n-type wells 71 and 72, and the p-type silicon substrate 70 is biased to the ground level. An input terminal 60 is connected to the p-type impurity region 75 in the n-type well 72 and the n-type impurity region 74 in the n-type well 71. The p-type impurity region 75 and the n-type well 72 form a diode 61, and the p-type silicon substrate 70 and the n-type well 71 form another diode 62. Thus, the two vertical diodes 61 and 62 are connected between the input terminal 60 and the power supply PW and between the input terminal 60 and the ground line GND as shown in FIG. 3, and offer discharging paths to the power supply line PW and the ground line GND.
When static charge is applied to the input terminal 60, the prior art vertical diodes 61/62 discharge the static charge current to the power supply line PW or the ground line GND, and protect circuit components such as metal-insulator-semiconductor type field effect transistors against the static charge. However, the prior art vertical diodes 61/62 hardly protect miniature metal-insulator-semiconductor type field effect transistors against the static charge. In fact, the static charge is liable to damage the gate insulators of the miniature metal-insulator-semiconductor type field effect transistors.
It is therefore an important object of the present invention to provide a protection circuit, which effectively prevents circuit components designed under 0.5 micron rules or less from static charge.
It is also an important object of the present invention to provide a process for fabricating the protection circuit.
The present inventor contemplated the problem inherent in the prior art vertical diodes 61/62, and noticed that the miniaturization resulted in the gate voltage higher than the clamp voltage of the vertical diodes 61/62. In detail, FIG. 4 illustrated the voltage-to-current characteristics of the prior art vertical diodes 61/62. When static charge was applied to the input terminal 60, the vertical diode 62 started to flow static charge current at a breakdown voltage V1, and the amount of current was increased together with the static voltage. When the prior art semiconductor integrated circuit was designed under 0.5 micron rules, the breakdown voltage V1 was 8 volts to 10 volts, and was approximately equal to the breakdown voltage of metal-insulator-semiconductor type field effect transistors of an input circuit to be protected. If the static charge current was Id, the gate voltage was increased to V2, and the gate voltage V2 was higher than the breakdown voltage V1. Thus, the voltage V2 higher than the breakdown voltage V1 was applied to the gate electrodes of the metal-insulator-semiconductor type field effect transistors, and the high voltage V2 was liable to damage the gate insulators of the field effect transistors.
To accomplish the object, the present invention proposes to reduce a base resistance.
In accordance with one aspect of the present invention, there is provided a semiconductor integrated circuit device fabricated on a semiconductor substrate of one conductivity type, and the semiconductor integrated circuit device comprises shallow trench isolating regions having a first depth and formed in surface portions of the semiconductor substrate for defining active areas therebetween, a terminal formed on the semiconductor substrate and unavoidably applied with static charge, a circuit component of an integrated circuit formed in one of the active areas and connected between the terminal and a first source of constant voltage and a protection circuit protecting the circuit component from the static charge, formed in at least the aforesaid one of the active areas and including a first impurity region of the aforesaid one conductivity type formed under the aforesaid at least one of the active areas and serving as a base region of a bipolar transistor, a second impurity region of the other conductivity type opposite to the aforesaid one conductivity type formed in a surface portion of the first impurity region, connected to the terminal and serving as one of an emitter region and a collector region of the bipolar transistor and a third impurity region of the other conductivity type connected to a second source of constant voltage, formed in another surface portion of the semiconductor substrate in such a manner that static charge flows through the first impurity region without substantial resistance due to the shallow trench isolating regions and serving as the other of the emitter region and the collector region of the bipolar transistor.
In accordance with another aspect of the present invention, there is provided a process for fabricating a semiconductor integrated circuit device comprising the steps of a) preparing a semiconductor substrate having one conductivity type, b) introducing a first dopant impurity into a surface portion of the semiconductor substrate for forming a first impurity region of the other conductivity type opposite to the one conductivity type, c) introducing a second dopant impurity into a surface portion of the first impurity region for forming a second impurity region shallower than the first impurity region and having the one conductivity type, d) forming a groove shallower than the second impurity region in a surface portion of the second impurity region, e) filling the groove with insulating material for forming a shallow trench isolating region and f) introducing a third dopant impurity into another surface portion of the second impurity region for forming a third impurity region of the one conductivity type shallower than the second impurity region, the first impurity region, the second impurity region and the third impurity region serving as an emitter region, a base region and a collector region of a vertical bipolar transistor for discharging static charge current applied to a terminal connected to the third impurity region.